FIG. 1 illustrates an exemplary N-stage pipelined ADC 100 that is known in the art. The pipelined ADC 100 may include a number of cascaded multiplying digital-to-analog converter (MDAC) stages 102-108 and a control and correction logic circuit 110. The pipeline ADC 100 may receive an analog input signal vin at an input of the first stage 102 and eventually produce a digital output Dout that corresponds to vin. In operation, each stage of the pipelined ADC may be responsible for converting a portion of the input signal vin into a digital code and pass along a remaining portion of the input signal to a next stage of conversion. For example, stage i 106 may receive an input signal Vi-1 and convert the input signal into an n-bit digital code Di and output a remaining portion Vi of the input Vi-1 to the next stage i+1. The n-bit digital code Di may be a one-bit digital code, or a digital code of more than one bit. The control and correction logic 110 may receive the digital codes D1, D2, . . . , Di, . . . , Dn sequentially through a series of clock cycles (not shown) and assemble these digital codes into the digital output Dout. The assembling may include inserting appropriate delays and bit shifts. Further, the control and correction login 110 may correct digital errors.
FIG. 2 illustrates an exemplary MDAC stage 200. The exemplary stage (stage k) may include an analog-to-digital converter (ADC) 202, a digital-to-analog converter (DAC) 204, a summing node 206, and an amplifier 208. The MDAC stage 200 may receive an input signal vk-1 from the output of a previous stage which may correspond to a remaining portion of the input signal Vk-1 after k−1 MDAC stages of processing. When k=1 at stage one, the input signal may be the analog input to the pipelined ADC. The input signal yk-1 may be, via a first signal path, fed to the ADC 202 for converting yk-1 into a digital code Dk which may be provided to the control and correction logic circuit 110. The input signal vk-1 may also be, via a second signal path, fed to a first input of the summing node 206. The digital code Dk may also be fed to the DAC 204 which may convert the digital code Dk into an analog signal VDk that represents an analog value for the digital code Dk. The analog signal VDk may be fed into a second input of the summing node 206 so that the summing node 206 may subtract the analog signal VDk from the input signal vk to form a difference signal. The difference signal may be scaled by the amplifier 208 to produce a remaining output Vk for a following MDAC stage.
FIG. 3 illustrates an exemplary schematic of the MDAC stage as shown in FIG. 2. The illustrated MDAC stage is for one-bit conversion. However, multiple bit MDAC stages may be similarly constructed. Referring to FIG. 3, the MDAC stage circuit 300 may include a 1-bit flash ADC 302, a DAC 306, an amplifier 312, an input capacitor 310, a feedback capacitor 316, and switches 308, 314, 318. The flash 302 may include a comparator circuit 304 that may include a first input for receiving an input signal Vk-1 and a second input being coupled to a reference. The comparator 304 may compare the input signal Vk-1 with the reference and generate a one-bit digital code D0 based on the comparison. For example, the comparator 304 may produce a “1” if the input signal Vk-1 is higher than the reference or a “0” if the input signal Vk-1 is lower than the reference. The digital code D0 may be provided to a control and correction logic and to a DAC 306. The control and correction circuit, as discussed above, may assemble digital codes from all of the stages to form the eventual digital output for the pipelined ADC. The DAC 306 may convert the digital code D0 into an analog signal VD0 which may be supplied via the input capacitor 310 to a summing node SN. The DAC 306 may further include one or more capacitors (not shown) and switches (not shown) to control these DAC capacitors. A first input of the amplifier 312 may be coupled to the summing node SN, and a second input may be coupled to a reference voltage. The feedback capacitor 316 may be coupled from the summing node to an output of the amplifier 312. Further, the input signal Vk-1 may be, via switch 308, selectively connected to the input capacitor 310, the summing node may be, via switch 314, selectively connected to a reference, and the output Vk may be, via switch 318, selectively connected to a reference.
FIG. 4 further illustrates an exemplary schematic of a comparator 400. The exemplary comparator 400 may include a pre-amplifier 402 and a latch 404 coupled to an output of the pre-amplifier 402. The pre-amplifier 402 may include a first input for receiving the input signal Vk-1 and a second input being coupled to a reference. The pre-amplifier 402 may amplify a difference signal between the input Vk-1 and the reference, and supply the amplified difference signal to the latch 404. The latch 404 may be a latch circuit commonly known in the art that operates according to a clock to produce differential outputs Vout+ and Vout−. In operation, the latch 404 may receive the difference signal from the pre-amplifier and operate according to the clock. The clock supplied to the latch 404 may be composed of a series of clock cycles that each further includes a first high phase (“1”) and a second low phase (“0”). Thus, when the clock is a high phase, the latch 404 may operate to keep the latch from regenerating so that the outputs Vout+ and Vout− may maintain a difference. When the clock is in a low phase, an internal positive feedback loop in the latch 404 may force the differential outputs Vout+ and Vout− to transition into a stable state depending on the differential input. The transition is commonly called regeneration whose temporal length may be dependent on the voltage difference between Vout+ and Vout−. Thus, a smaller voltage difference may need longer time or longer regeneration time to achieve a stable state, and a larger voltage difference may need shorter time or shorter regeneration time.
During operation, stages of the pipelined ADC as illustrated in FIG. 3 may operate according to an ADC clock (ADC CLK) as illustrated in FIG. 5. The ADC clock may include a sequence of clock cycles such as C1, C2. Each clock cycle may further include a first phase P1 and a second P2 in which P1 and P2 may indicate a respective low level and high level of the ADC clock. During the first phase P1 of the ADC clock, switches 308, 314, 318 may be engaged so that the input signal Vk-1 may be charged to the input capacitor 310, and the feedback capacitor 316 may be discharged. This first phase is also called the sample phase as the input capacitor samples input signal. During the sample phase, the comparator 304 may be in a tracking state under which the latch in the comparator is kept from regenerating. Also, during the sample phase, a switch in the DAC (not shown) may be disengaged such that the DAC is decoupled from the input capacitor 310. In an alternative implementation, DAC 306 may include one or more capacitors (not shown) that are separate from capacitor 310. These separate capacitors may include a first end coupled to the summing node (SN) and a second end coupled to a reference (0V) during the sample phase.
Following the sample phase, the ADC clock may enter a second phase of the clock cycle called a gain phase. During the gain phase, switches 308, 314, 318 may be disengaged, and internal switches (not shown) in DAC 306 may be engaged so that the DAC 306 may be coupled to the input capacitor 310. Thus, during the gain phase, the latch in the comparator 304 may be switched on to start regenerating. Further, the charge on the input capacitor 310 minus the output from DAC 306 may be transferred, via the feedback capacitor 316, to the output. The capacitance ratio between the feedback capacitor 316 and the input capacitor 310 may determine a gain ratio at the output Vk. However, as discussed above, the regenerating at the latch may take time treg whose length depends on the output voltage difference at the latch. Further, the capacitors in DAC 306 may also take time tdr to be driven to proper charges. The combined time treg+tdr occurs during the gain phase and reduces the stable output time tg of the output signal Vout.
In other designs, other considerations may further reduce the time tg of stable output in addition to treg and tdr. For example, U.S. patent application Ser. No. 12/578,057 ('057 Application) of the assignee of the present application describes four input channels that share a single amplifier and a single feedback capacitor. Thus, following the gain phase of another channel (which may occur during a sample phase of the current channel), the shared feedback capacitor and DAC capacitors may need to be discharged prior to being used by the current channel. Since the feedback capacitor 316 is directly coupled to the output of the amplifier 312, the output of the amplifier 312 may need to clamp to 0V. This reset operation also occurs during the gain phase and may take additional time trs away from the amplifier gain settling to a stable output.
Larger and faster drivers may reduce treg, tdr, and trs. However, larger and faster drivers may require a larger amplifier and a large comparator which consume more power.